1. Field of the Invention
The present invention generally relates to computer architecture.
2. Description of Related Art
Conventional computer architecture typically includes a single bus that couples a microprocessor with memory and Input/Output (I/O) devices. The bus carries a number of electrical signals between the various components of the system. The speed of the signals is somewhat dictated by the length of the bus. High speed signals are difficult to send over long distances, because of the cross inductance between bus lines. Generally speaking, higher frequencies require shorter bus lines.
I/O ports are typically located on a separate card, whereby the signals must travel through connectors and various printed circuit boards to communicate with of the processor. This limits the speed of the bus and degrades the performance of the processor. The bus speed also controls the rate of data transfer between the processor and memory devices. It is generally desirable to have high data rates between the processor and memory. Usually an increase in data rate requires a larger number of pins on the chip. Adding pins enlarges the size of the chip, increasing the cost and complexity of the same. It would therefore be desirable to have a high speed memory bus that would provide a high data rate with a minimal amount of pins. It would also be desirable to have an architecture that would allow such a high speed bus to operate independently of the I/O devices of the system.
Microprocessors are constantly being redesigned to run at faster clock rates. Usually the development of faster CPU devices require the addition of hardware and/or software, so that the existing system can interface with the new processor. This is particularly true for the interface between the processor and the bus, which contains existing I/O devices that run at the slower data rate. Recent systems have incorporated various levels of cache memory to compensate for the slow data rate between the processor and main memory. Additionally, cache requires additional components, thereby increasing the cost and complexity of the system. It would therefore be desirable to have an architecture that would allow faster processors to be installed into existing systems, without having to drastically change the existing hardware and software of the system.